The Ware for March 2013 is shown below. Click on the image for a larger version.
Thanks to Patricio Worthalter for contributing this month’s ware! The PCI Matchmaker from AMCC brings me back. I used one of those as part of my Master’s thesis, back in the day when FPGAs accessible by mere mortals couldn’t do PCI directly. Man, it was (and still is) a pain to properly obtain the official PCI bus specs…PCI is a member’s-only club, with a $3k annual fee. Ain’t nobody got dime fo’ that!
It smells like a PCI data acquisition card of some type. Something about the circuitry next to the connector makes me think that.
Option 2 is some form of programmable card for something, judging only by the fact that one of the headers has been partially used for a connector.
The 16552 and stack of 26LS31 line drivers strongly suggests a 16-port RS-422 card, don’t they… but it’s odd to have no receivers, and why the FPGA then?
I’m gonna go with external SCSI card, narrow low-voltage differential, probably 10-20MB/sec, but the 26LS31 is IMHO a shade short on margin for 40MB/sec. Given the well-aged look of it, lack of bespoke parts and the seemingly superfluous 16552, I’d say it was probably designed specifically for a high-ticket item like a film scanner or typesetter.
There is an Altera chip form the MAX 9000 series, 9320A seems to be a small CPLD with 320 marocells:
http://www.altera.com/products/devices/max9k/m9k-index.html
As hinted, the AMCC chip seems to provide PCI functionality. 5933 PCI Matchmaker
I found a FLINK data protocol description from ’99 that probably used this board, some other posts hint at ’97
A newer model of the AMCC PCI eval kit provides add-on bus, rs232 and SRAM mapping.
I doubt the small CPLD (smallet of the family) is able to speak SCSI.
The FLINK data protocol would require receivers as well – unlikely.
Similarly, an amcc 5933 eval kit would need inputs, an amcc-based ISA adapter card is also lacking inputs.
I bet the diff receivers are hidden in the FPGA. Or, they just fake it and ignore one or the other half of the pair.
You should check out the datasheet for the 53C80 SCSI bus adapter to see just how little hardware it takes to add a SCSI interface to a system. That modest FPGA could easily handle SCSI layer 1 and most of 2, plus the memory bus, host bus, address counters, differential receivers, whatever that DUART is there for and all the rest of the glue, calling upon the host computer to help out with what’s left of layer 2 and the layers above.
40 rather big inductors near the HD edge connector (which is 50pin) means that almost every pin/signal is (by todays standards) low-speed.
U7, U9, U11, U12 are AM26LS31C QUADRUPLE DIFFERENTIAL LINE DRIVER, so we have 16 pairs, 32 signals in total. Outputs are wired towards the HD connector.
ISO01 and ISO02 are “high-speed” dual channel optocouplers, good for 10Mhz. The output goes toward the HD connector.
PC16552 is a UART, clocked by a 3,68 MHz oscillator.
CY7C433 is a 4k * 9bit asynchronous fifo. (two times)
CY7C199 is a 32K x 8 Static RAM. (two times)
The FPGA is a Altera MAX9000 (320 macrocells, 6000 gates, 168 user-pins (max)).
This is all generic enough, that to me it doesn’t give enough hints about the particular function of the card, but… I’ve worked in experimental particle physics for a long time, and there we had a lot of specialized hardware, of which a card like this very much reminds me of.
Today’s board:
– Has a PCI interface, and 8kByte of hardware async fifo: So the card needs serious buffering, hence is expected to process some larger amounts of data, with some kind of realtime/no-underrun guarantee, possibly bridging two clocking domains. Also has 64kByte of RAM.
– Is (as far as I can see) mostly output only (16 pairs).
– Has four opto-isolated outputs, but no obvious means to create a galvanically isolated voltage, hende whatever it connects to is self-powered.
If I had found this card in the context of particle-physics, I’d guess that it creates some kind of control/trigger signals for controlling some apparatus at a considerable distance (because of the differential signalling).
From looking at the FIFO pins: The FIFO outputs seem to be connected to 24pin header J2, 48pin J3 has all address and data signals of FIFOs, UART and SRAMs.
Interestingly J2 seems to have 12 FIFO outputs in order (Q0..Q7, then again Q0..Q3) on only the even numbered pins, why would one use such a pinout? Maybe for having a long cable with alternating grounds to make sure there are less problems with signal quality?
It reminds me an HP-IB/GPIB/IEEE-488 interface.
SCSI?
Found a similar board on ebay
PWA COPCIL 6E7328 REV A 74-0401-7294-7 REV-A:
I think it is a generic board used for driving medical equipments (laser imager), integrated in the PACS LINK 9410 ACQUISITION SYSTEM from Kodak, with a configuration file for each equipment.
I’m guessing some sort of dedicated cluster interconnect card.
Maybe for SGI Octane or Sun servers.
I found this link: http://www.scribd.com/doc/7300719/Phillips-Setup-Manuals?
On page 8: Seems like a RS422 interface board that can interface to a printer. In this doc, it was used between a Kodak 9410 and a Kodak DryView (x-ray printer) as part of a DICOM network. The pinout specifies 9 pins for control, and 37 pins for data, which fits the 50 pin connector with a few spares.
Going by others’ analysis, I’d say it’s the receiving end for a MRI machine
Julien Lefort and Jeff got it right. The card was pulled from a PacsLink (not a 9410 though). It’s funny to see that this time “the googlers” outplaced the electronic-savvy folks.
Thanks everyone for your time.
So, is the BUS on the left side transmit only, or bi-directional?
That’s odd, my system thought is was 06:41 am on the 24th when I sent the previous reply.
What time zone is being used for the display time?
arargh
it´s a wide scsi pci card.