The Ware for February 2010 is shown below. Click on the photo for a much larger version.

This is yet another mobile phone PCB blank of unknown origin. It’s nice that the layout of the PCB tiling reveals both the top and bottom sides in the same panel, and it’s interesting to note the impedance test coupons going down the center spine. Like the previous mobile phone PCBs featured on Name that Ware, I suspect this is from an HTC design, but that’s about all I know about it. Curious to find out what product this is from, I’m betting someone out there will know!

The Ware for January 2010 was a 2Gbyte microSD card. Below is an image of the whole card, with the area that was shown in the contest photo circled in black.

The region imaged for the contest is about 1/8th to 1/16th of the whole card; with a capacity of 16 billion bits, the imaged region of the FLASH chip alone is therefore showing at least a billion transistors. The lighter-colored region in the center of the FLASH chip is where I nicked the die prior to acid etching as I was grinding the package. I’ve since learned that grinding is unnecessary for microSD cards. :-)

MicroSD cards are wholly amazing devices (XKCD seems to share my sentiment on this), not simply because of their great storage to size ratio, but also because of their internal construction. I was a little surprised by two things: first, the use of stacked CSP (chip scale package) construction, and second, the sheer size of the FLASH die.

To do the CSP in such a thin package, both die (the FLASH and the controller) have to be thinned. Before each wafer is diced, they are flipped over and mechanically polished. The controller die in particular looks to be polished to a thickness of about 0.1mm — near the width of a human hair.

For the FLASH die, I was a bit surprised by how large it was. Before decapsulating the card, I was expecting to see one of two things: perhaps two die side by side, with the memory chip maybe about 6-7mm on a side and a 3mm/edge controller chip next to it, or a single fully-integrated FLASH + controller die. Instead, the memory chip is about 9 x 13mm — filling nearly the entire package edge to edge — and the controller chip is a sliver of silicon only 1.5mm wide and a shy more than 4mm long. Also, the actual FLASH chip die is simply a K9GAG08U0D, which is a common MLC device that you can also purchase in a TSOP package.

This is pretty clever on Samsung’s part. By sizing their commodity street FLASH to fit inside a microSD card, they are able to feather demand between popular SKUs. It’s also amusing that a full 32-bit ARM core is used as the controller between the FLASH device and the SD card interface. The world is just crawling with ARM controllers…

As for the winner, a bit tough to pick this time. A lot of people walked around the answer, thrown off by the CMP fill tiles, and assuming the device had something to do with a secure system.

The metal squares, while they do obscure the circuitry beneath them, are not active elements nor are they put there for the purpose of security. They are there actually to ensure that the fill density of metal versus dielectric is within a certain ratio. This is due to a requirement of a process known as CMP (chemical-mechanical polishing), where a chip’s active surface is planarized, layer by layer, by rubbing abrasive pads with a fine-grit chemical slurry across the surface. If the fill ratio is not obeyed, then portions outside the ratio will either polish too quickly or too slowly due to the differential in hardness between the metal and the oxide dielectric, and the result will be a non-planar surface.

You can see the fill density equalization going on in the picture above. The very large silvery tiles are from a very coarse top layer metal used just for bonding pads. The copper-hued tiles are from a lower wiring layer. You can see just a few of those wires in this photo. The area immediately around the wire has no tiling, but the otherwise open expanse is entirely filled in to ensure that the sparse, tiny wires don’t get polished away during the CMP operation.

Thus, when you see CMP tiling you know you are dealing with a deep submicron process with a lot of metal layers. Also, active protection meshes typically do not use unconnected pieces of metal; instead, the metal is connected in a series chain so damage to any individual element is easily detected by the monitoring circuit.

Since MegabytePhreak is the first answer to use the term “microSD” explicitly, he/she is the winner (by just 3 hours over Burlap). Congrats! email me for your prize.

The Ware for January 2010 is shown below.

Is it really already 2010? Yikes. Almost 5 years running now with Name That Ware. Maybe I should make a nice color pin-up calendar of select wares for next year.

This is, of course, just a selected corner of the whole ware. I’ll give a hint: unlike last month’s ware, this is a very common ware.

[Added 1/27/10]

Looks like maybe I didn’t give enough hints. Here’s a couple more:

Above is a shot of the die marking on the top chip (S3C49VDX-02S). The bond pads at the bottom give you a sense of scale (click on the photo for a much larger version).

Some other thoughts and observations:

The Ware for December 2009 is the active element of a Tektronix P7350 5GHz Differential probe, photos courtesy of tmbinc. It’s a $7,000 oscilloscope probe, and the technology inside of it is exquisite. From the high frequency ceramic substrate to the wirebonded decoupling capacitors, no expense was spared in making the probe. I can only speculate what kind of technology is used for the IC in the center of the photo; it looks like it has gold metallization, which is unusual to see on any silicon process since gold contamination causes a deep-level trap defect in silicon. That leads me to think maybe it’s a III-V (i.e., GaAs or InP) process where gold is more common. On the other hand, Brian points out that the backside is biased, which isn’t something you’d require if the devices were fabbed using the common semi-insulating substrate technique employed on many III-V designs.

Above: an image of almost the entire probe circuit. There’s another fragment that would be to the left that is also missing. I feel compelled to note that tmbinc (the photographer for this ware) didn’t break the probe; he bought it broken for cheap.

I’ve been a long time fan of Tek products; their engineers are hard-core and I typically learn something new every time I take the hood off of one of their devices. Back when digital scopes came into being, Tek made the only respectable digital scope (in my opinion) because they understood that the integrating behavior of phosphors in analog scopes was actually a desirable effect, a feature so important that they gave it a name: Digital Phosphor Technology. The other thing Tek did really Right was to keep all the old analog-ish knobs on their panels. Back in the analog days you had all sorts of trim, sweep, scale, trigger, etc. knobs that were a direct part of the oscilloscope’s analog circuitry. Of course, when we transitioned into the digital world, there was no more essential requirement for all these knobs. Agilent went so far as to create digital oscilloscopes (like the 54120) with a single jog dial that was modal. Everytime you wanted to switch from adjusting the timebase or amplitude scales, you had to reprogram the knob’s mode by hitting a couple buttons. It was a terrible UI that really killed productivity, but I imagine some product manager at Agilent must have thought he or she was really clever for optimizing the complex and expensive analog oscilloscope UI down to a single knob. The Tek digital scopes, on the other hand, had a bank of buttons almost exactly like they had on their analog scopes, so the tool had a great hand feel to it.

Anyways, back to the competition. The winner is Brian! Very impressive deduction skills, I was thinking this might have been a real stumper (I know I wouldn’t have guessed it), but again I was proven wrong. Email me to claim your prize!