Field Programmable Clock (FPC)

The Field Programmable Clock (FPC) features a digital frequency synthesizer PLL that is user programmable. Programming occurs via a two-wire serial interface consisting of one clock and one data wire. The PLL uses a 10 MHz crystal oscillator as a reference frequency source. The simple two-wire programming interface makes the FPC ideal for use with FPGAs where user pin count budgets often cannot afford a parallel programming interface.

The FPC's pinout is backward-compatible with the industry standard 14-pin DIP oscillator pinout; one can plug a fixed frequency oscillator into an FPC socket once a design is mature and the operating frequency is set.

Upon power up, the FPC will output a 10 MHz clock until configured by the host. A typical FPC application would integrate an FPC programming state machine into the user's design. This state machine is activated after FPGA configuration; the 10 MHz default frequency allows the FPGA-FPC system to bootstrap itself into the desired operating frequency. The PLL can be configured in a manner which provides a glitch-free transition between the default frequency and the programmed frequency.

It is important that proper decoupling is provided across the power feed into the FPC, as PLL stability can be affected by power line noise. It is also important that Vcc have a clean, monotonic rise of less than 5 ms to spec upon power up in order to prevent the PLL from locking up.

Please see the companion data sheet, Cypress Semiconductor ICD2053B Programmable Clock Generator, Cypress document #38-00412, for further information about programming the FPC. The FPC has the same programming interface as the ICD2053B. Cypress offers a program, BITCALC, which can assist users in calculating PLL parameters.

Operating Conditions

Electrical Characteristics

Switching Characteristics

Mechanical Characteristics