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Reconfigurable Hardware Processor (RHP) Technology is a new computer architecture where software algorithms are implemented directly in hardware, thus avoiding the performance penalties associated with the classical vonNeumann architectures (such as the Pentium or the DEC Alpha) which strives to use one piece of hardware to solve all problems using a stored program architecture.

To better understand the significance of RHPs, some historical background is required. In John vonNeumann's (1903-1957) time, the lack of highly integrated electronics and design tools made the cost and engineering effort of creating a piece of application-specific hardware prohibitavely high. vonNeumann's solution was to create a general purpose processor (GPP) that could be instructed to do a set of simple operations through a program that was temporarily stored in memory. Complex operations could be broken down into a series of these simple operations, or instructions. The more complex the problem, the bigger the program and the more time it took to execute the program.

In other words, the GPP represents a cost-performance compromise: you gain generality and ease of re-use at the price of having to break operations down into a long string of simple instructions that are stored, fetched, and interpreted.

The RHP is not restricted by this compromise yet it is comparable in cost to conventional GPPs. This is because in an RHP, the hardware uses "soft wires" that are rewired for each application. In other words, complex operations can be directly implemented in hardware without having to be broken into instructions; thus there is no overhead of having to fetch, decode, schedule and interpret instructions.

Think of it as an analogy with travel: suppose you want to get from San Francisco to Boston. In the GPP model, you have to take a taxi to the airport, then you have to take MD-10 to O'Hare, and then you have to take a 757 to Boston logan, after which you hop on the subway to get to your ultimate destination. Your trip was broken down into several segments, and each segment required you to wait for specific equipment to arrive and pick you up. In the RHP model, you ride a single vehicle which transforms from a car into an airplane when you need it, and you can travel from San Francisco to Boston non-stop.

Sounds like fantasy? In the world of transportation, it is. However, in the world of computers, it's a reality available today. Since vonNeumann's time, computers have gotten smaller, cheaper, and faster. Recent advances in silicon processing has allowed us to economically embed switching networks in the wiring of chips ("soft wires") and create large arrays of configurable logic. This technology of configurable logic plus configurable wiring is the basis of all RHPs. By modifying the configuration of the wires and the logic one can implement a wide variety of algorithms directly in hardware.

In fact, the next generation of silicon processing places RHPs in an excellent position to gain a persuasive lead on GPPs. With more transistors available on a chip, and with wire delays becoming a dominant factor in high-speed designs, GPP designers are finding it difficult to utilize the entire piece of silicon in an efficient manner. Traditional superscalar microprocessors hit a performance wall in part because only so many instructions can be issued per clock cycle and also because large designs with many execution units are slowed down by the long wires required to span the chip. Although vendors such as Intel are moving to VLIW architectures (EPIC in Intel-marketese) to try and extend the life of the GPP, RHPs are inherently scalable to very large designs. This is because RHPs do not have to rely on central register files or I-caches and are thus saved from the increasing wire delays. RHPs also have an inherent parallelism that is free from resource starvation: every operation in an algorithm gets its own computational resources, as opposed to the GPP situation where if all the execution units are busy or if the register file is saturated, execution must halt.

Thus, RHPs offer advantages over GPPs in the way that the overhead of fetching, scheduling, and executing instructions is minimized by the direct implementation of algorithms in hardware. RHPs also offer an advantage over GPPs in the future because the RHP architecture is better suited for the unique challenges of deep-submicron IC design.